Researchers develop flexible, stretchable photonic devices
Light-based devices could be used as biomedical sensors or as flexible connectors for electronics.
Using chip memory more efficiently
System for generating ad hoc “cache hierarchies” increases processing speed while reducing energy consumption.
Practical parallelism
System enables large speedups — as much as 88-fold — on common parallel-computing algorithms.
A big leap toward tinier lines
Self-assembly technique could lead to long-awaited, simple method for making smaller microchip patterns.
Commercializing integrated photonics
AIM Photonics fall meeting attendees tackle plans for making computer chips with integrated optical devices and developing a regional workforce.
Cache management improved once again
New version of breakthrough memory management scheme better accommodates commercial chips.
Toward hack-proof RFID chips
New technology could secure credit cards, key cards, and pallets of goods in warehouses.
Self-stacking nanogrids
Polymer nanowires that assemble in perpendicular layers could offer route to tinier chip components.
First new cache-coherence mechanism in 30 years
More efficient memory-management scheme could help enable chips with thousands of cores.
Silicon photonics meets the foundry
Lionel Kimerling, Rajeev Ram, and other MIT researchers explore practical ways to bring optical interconnection toward and directly onto chips.
Smarter multicore chips
New approach to distributing computations could make multicore chips much faster.
Researchers unveil experimental 36-core chip
Design lets chip manage local memory stores efficiently using an Internet-style communication network.
Parallel programming may not be so daunting
“Lock-free” parallel algorithms may match performance of more complex “wait-free” algorithms.
Smarter caching
Cleverer management of the local memory banks known as ‘caches’ could improve computer chips’ performance while reducing their energy consumption.
How to program unreliable chips
A new language lets coders reason about the trade-off between fidelity of execution and power or time savings in the computers of the future.