Simulating tomorrow’s chips
A new system makes hardware models of multicore chips more efficient, easier to design and more reliable.
A new system makes hardware models of multicore chips more efficient, easier to design and more reliable.
The data-routing techniques that undergird the Internet could increase the efficiency of multicore chips while lowering their power requirements.
A new software-simulation system promises much more accurate evaluation of promising — but potentially fault-ridden — multicore-chip designs.
Aims to become the world’s premier scholarly hub for technologically intensive design.
Alumnus Michael Pasqual and professor Olivier de Weck win ‘Reviewers’ Favorite’ award
Flexibility in Engineering Design by Richard de Neufville and Stefan Scholtes now available.